Key facts
- Start date
- 1 June 2026
- End date
- 31 May 2029
- Funded by
- Chips JU
- Partners
- 24 organizations
- Total cost
- €14,537,084
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ODE4EC-PIV
ODE4EC-PIV targets open source tools for productivity of chip design, integration into flows and verification.
Focus
Open source chip design has reached the point where the individual tools are capable, but the path from an idea to a verified design still asks too much of the engineer walking it. Tools do not always agree on formats, flows have to be reassembled by hand for every project, and verification environments rarely meet the expectations that industrial teams bring with them. ODE4EC-PIV works on that seam of the ecosystem rather than on any single tool, so that what already exists becomes something a team can actually adopt.
The work is organised around three concerns that reinforce each other. Productivity covers design entry, IP management and generator-based flows, along with the waveform and analysis tooling that engineers spend their days in. Interoperability covers the modular frameworks, standardised interfaces and open data exchange formats that let heterogeneous tools hand work to each other without a custom script in between. Verification covers formal methods, UVM-inspired and Python-based environments, hardware and software co-simulation, and the continuous integration practice that keeps all of it honest as designs evolve.
Everything the project builds is evaluated against real use cases contributed by the consortium and released openly, so the results are usable beyond the lifetime of the grant.
Objectives
Efficiency
Advanced verification and waveform analysis across analogue, digital and mixed-signal domains, for faster and more accurate design iterations.
Interoperability
Modular frameworks, standardised interfaces and open data exchange guidelines that let heterogeneous tools work together.
Accessibility
Better usability of open source EDA tools, support for industry-standard verification methodologies, and curated toolchains for IP generation.
Demonstrators
Validation of the tools and methodologies in industry-relevant demonstrators, benchmarked against current practice.
Market uptake
Engagement across the semiconductor value chain, industrial pilots, and integration of project results into existing CI/CD-based design environments.
Sovereignty
Open, standards-based design infrastructure in the critical stages of the EDA flow, reducing reliance on non-European solutions.
Work packages
| WP | Title | Lead |
|---|---|---|
| WP1 | Use Cases and Evaluation | E4 Computer Engineering |
| WP2 | Modular Frameworks for Design Entry and Flow Integration | HM University of Applied Sciences Munich |
| WP3 | Industry-Standard Verification | Barcelona Supercomputing Center |
| WP4 | AI-Driven Novel Methodologies for Hardware Design | Politecnico di Torino |
| WP5 | Dissemination, Exploitation, and Ecosystem Sustainability | Politecnico di Milano |
| WP6 | Project Management | INESC TEC |